Vector bus – a 4-bit address bus that can be used to trigger a specific table output form the I/O module.  The 4 bits may be user selected from any of the 96 channels of a particular timing generator group.  The data will be output on the next data cycle after receipt of the vector address

Handshake bus – allows the user to select any of the 192 channels as a test input for the timing generator.  Inputs may be tested for high, low, rising or falling edges.  Two channels on each timing generator may be selected as test input channels during any test

Clock Resolution – The SR101A timing module may be clocked on both edges of the system clock allowing for better timing set resolution

Timing Set Clock – a new programmable clock source has been added to the SR101A

Strobes/Enables – the number of strobes/enables has been increased from 4 to 6

SR124A – 8 channels of bi-directional TTL or RS422/RS485

SR125A – 16 channels of bi-directional TTL

SR126A – 8 channels of bi-directional LVDS

SR214A – 16 channels of bi-directional variable voltage (+7VDC to –5VDC)

8 to 192 I/O channels per SR192A (2 VXI Slots)

Multiple SR192A modules may be linked to provide up to 1152 channels

Mix and match different logic family modules within the SR192A

I/O module types include: Variable voltage (+7VDC to -5VDC, TTL, RS485, LVDS)

Data rates from .01Hz to 50Mhz

4 bit vector bus

Handshake bus

Internal clock source (8Hz to 100Mhz) or external clock input

6 input strobes or output enables per timing module (maximum of 2 timing modules per SR192A)

Input strobe/output enables delay (0 – 20ns at 1ns increment, to compensate for cable delay, etc.)

I/O module data formatting (RTO, RTZ, RTC and Hold)

4 operating modes (parallel, serial, multiplex and increment)

256K I/O memory depth (input/output vectors)

Per pin enable/tristate

Variable voltage levels assigned in 8 pin groups

High speed parallel UUT testing

Serial UUT testing (up to 24Mbits)

Bus emulation

Stimulus/response